6709 search results - page 927 / 1342 » Performance Modelling of the Computational Hardware: A Stati... |
230
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FPL
2010
Springer
15 years 5 months ago
2010
Springer
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
220
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CISS
2010
IEEE
14 years 11 months ago
2010
IEEE
Abstract—Compressive sampling (CS) has emerged as significant signal processing framework to acquire and reconstruct sparse signals at rates significantly below the Nyquist rate...
177
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DATE
2007
IEEE
16 years 2 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
205
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IEEEPACT
2005
IEEE
16 years 1 months ago
2005
IEEE
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
179
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ISLPED
2000
ACM
16 years 1 days ago
2000
ACM
Quality of service (QoS) is one of the key features for new Internet-based multimedia and other applications. Meanwhile, energy remains as a big concern for systems that perform s...