151 search results - page 8 / 31 » Performance of Parallel Concatenated Coding Schemes |
135
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GLOBECOM
2006
IEEE
16 years 12 days ago
2006
IEEE
— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed thi...
168
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GLOBECOM
2006
IEEE
16 years 12 days ago
2006
IEEE
Abstract— This paper presents an Interleaver-Division Multiple Access (IDMA) based architecture with single-user decoding using parallel concatenated non-linear trellis codes (PC...
183
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SC
1995
ACM
15 years 10 months ago
1995
ACM
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
169
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DCC
2003
IEEE
16 years 6 months ago
2003
IEEE
Embedded computing systems are space and cost sensitive; memory is one of the most restricted resources, posing serious constraints on program size. Code compression, which is a s...
150
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ICC
2008
IEEE
16 years 24 days ago
2008
IEEE
— When channel state information (CSI) is available at both transmit and receive sides, singular value decomposition (SVD) converts the MIMO channel into parallel subchannels. It...