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    » Pipeline Vectorization for Reconfigurable Systems
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    152
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    IPPS
    2000
    IEEE
    94views Distributed And Parallel Com...» more  IPPS 2000»
    Fast Sorting on a Linear Array with a Reconfigurable Pipelined Bus System
    15 years 10 months ago
    Fast Sorting on a Linear Array with a Reconfigurable Pipelined Bus System
    Download  ipdps.cc.gatech.edu
    Amitava Datta, Robyn A. Owens, Subbiah Soundaralak...
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    184
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    IPPS
    2006
    IEEE
    124views Distributed And Parallel Com...» more  IPPS 2006»
    Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
    16 years 12 days ago
    Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
    Download  www.cecs.uci.edu
    A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
    Michalis D. Galanis, Grigoris Dimitroulakos, Const...
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    110
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    ISCAS
    1995
    IEEE
    109views Hardware» more  ISCAS 1995»
    System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit
    15 years 10 months ago
    System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit
    Download  www.cisl.columbia.edu
    Kevin J. Nowka, Michael J. Flynn
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    163
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    DAC
    2009
    ACM
    150views Computer Architecture» more  DAC 2009»
    A DVS-based pipelined reconfigurable instruction memory
    16 years 7 months ago
    A DVS-based pipelined reconfigurable instruction memory
    Download  esl.cse.nsysu.edu.tw
    Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
    Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
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    157
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    FCCM
    1999
    IEEE
    122views VLSI» more  FCCM 1999»
    Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
    15 years 10 months ago
    Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
    Download  www.ics.uci.edu
    Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
    Andrew A. Chien, Jay H. Byun
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