30 search results - page 1 / 6 » Pipelined Memory Shared Buffer for VLSI Switches |
144
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SIGCOMM
1995
ACM
15 years 10 months ago
1995
ACM
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perf...
147
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GLOBECOM
2006
IEEE
16 years 13 days ago
2006
IEEE
— Combined input-crosspoint buffered (CICB) packet switches with dedicated crosspoint buffers require a minimum amount of memory in the buffered crossbar of N2 × k × L, where N...
150
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HOTI
2005
IEEE
15 years 12 months ago
2005
IEEE
— The amount of memory in buffered crossbars in combined input-crosspoint buffered switches is proportional to the number of crosspoints, or O(N2 ), where N is the number of port...
197
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ISCA
2002
IEEE
15 years 11 months ago
2002
IEEE
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
180
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ASPLOS
1991
ACM
15 years 10 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...