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ARCS
2009
Springer
16 years 2 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
240
Voted
IPPS
2008
IEEE
16 years 2 months ago
High-speed string searching against large dictionaries on the Cell/B.E. Processor
Our digital universe is growing, creating exploding amounts of data which need to be searched, protected and filtered. String searching is at the core of the tools we use to curb...
Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Pe...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
16 years 2 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
SAMOS
2007
Springer
16 years 1 months ago
Online Prediction of Applications Cache Utility
— General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies a...
Miquel Moretó, Francisco J. Cazorla, Alex R...
VMCAI
2007
Springer
16 years 1 months ago
Lattice Automata
Abstract. Several verification methods involve reasoning about multi-valued systems, in which an atomic proposition is interpreted at a state as a lattice element, rather than a B...
Orna Kupferman, Yoad Lustig
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