7 search results - page 1 / 2 » Power supply variation effects on timing characteristics of ... |
166
Voted
ISCAS
2006
IEEE
16 years 1 months ago
2006
IEEE
— Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the tim...
168
Voted
GLVLSI
2006
IEEE
16 years 1 months ago
2006
IEEE
167
Voted
ISVLSI
2006
IEEE
16 years 1 months ago
2006
IEEE
— The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular...
195
Voted
ICCD
2001
IEEE
16 years 4 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
206
Voted
MICRO
2003
IEEE
16 years 21 days ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...