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VLSID
2002
IEEE
172views VLSI» more  VLSID 2002»
16 years 8 months ago
Improvement of ASIC Design Processes
With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this con...
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
ECBS
2006
IEEE
126views Hardware» more  ECBS 2006»
16 years 1 months ago
Experiments and Investigations for the Personal High Performance Computing (PHPC) built on top of the 64-bit processing and clus
The motivation and objective for this paper is to demonstrate “Personal High Performance Computing (PHPC)”, which requires only a smaller number of computers, resources and sp...
Victor Chang
ITCC
2002
IEEE
16 years 14 days ago
Audio Watermarking Quality Evaluation: Robustness to DA/AD Processes
Audio watermarking has become an important technology for recording and advertisement industry. Today’s embedding and detection strategies often rely on digital or at least high...
Martin Steinebach, Andreas Lang, Jana Dittmann, Ch...
SIGMETRICS
1993
ACM
15 years 11 months ago
The Process-Flow Model: Examining I/O Performance from the System's Point of View
Input/output subsystem performance is currently receiving considerable research attention. Signi cant e ort has been focused on reducing average I/O response times and increasing ...
Gregory R. Ganger, Yale N. Patt
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
15 years 9 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...