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» Processor Architectures for Ontogenesis
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DATE
2009
IEEE
113views Hardware» more  DATE 2009»
16 years 1 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
DSN
2007
IEEE
16 years 1 months ago
An Architectural Approach to Preventing Code Injection Attacks
Code injection attacks, despite being well researched, continue to be a problem today. Modern architectural solutions such as the NX-bit and PaX have been useful in limiting the a...
Ryan Riley, Xuxian Jiang, Dongyan Xu
169
Voted
DATE
2006
IEEE
171views Hardware» more  DATE 2006»
16 years 1 months ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...
IEEEPACT
2003
IEEE
16 years 8 days ago
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjee...
SP
1999
IEEE
125views Security Privacy» more  SP 1999»
15 years 11 months ago
A Multi-Threading Architecture for Multilevel Secure Transaction Processing
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design ...
Haruna R. Isa, William R. Shockley, Cynthia E. Irv...