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EUROPAR
2009
Springer
16 years 1 months ago
High Performance Matrix Multiplication on Many Cores
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
Nan Yuan, Yongbin Zhou, Guangming Tan, Junchao Zha...
IPPS
2003
IEEE
16 years 9 days ago
An Executable Analytical Performance Evaluation Approach for Early Performance Prediction
Percolation has recently been proposed as a key component of an advanced program execution model for future generation high-end machines featuring adaptive data/code transformatio...
Adeline Jacquet, Vincent Janot, Clement Leung, Gua...
ISORC
2000
IEEE
15 years 11 months ago
Hybrid Sequence Charts
We introduce Hybrid Sequence Charts (HySCs) as a visual description technique for communication in hybrid system models. To that end, we adapt a subset of the well-known MSC synta...
Radu Grosu, Ingolf Krüger, Thomas Stauner
CP
2006
Springer
15 years 10 months ago
Stochastic Allocation and Scheduling for Conditional Task Graphs in MPSoCs
This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph charac...
Michele Lombardi, Michela Milano
177
Voted
EUROPAR
2006
Springer
15 years 10 months ago
Specification of Inefficiency Patterns for MPI-2 One-Sided Communication
Abstract. Automatic performance analysis of parallel programs can be accomplished by scanning event traces of program execution for patterns representing inefficient behavior. The ...
Andrej Kühnal, Marc-André Hermanns, Be...