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LCTRTS
2007
Springer
16 years 1 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
SIGCSE
2009
ACM
167views Education» more  SIGCSE 2009»
16 years 8 months ago
Python CS1 as preparation for C++ CS2
How suitable is a Python-based CS1 course as preparation for a C++-based CS2 course? After fifteen years of using C++ for both CS1 and CS2, the Computer Science Department at Mich...
Richard J. Enbody, William F. Punch, Mark McCullen
ENTCS
2008
140views more  ENTCS 2008»
15 years 7 months ago
Higher-Order Separation Logic in Isabelle/HOLCF
We formalize higher-order separation logic for a first-order imperative language with procedures and local variables in Isabelle/HOLCF. The assertion language is modeled in such a...
Carsten Varming, Lars Birkedal
SIGCSE
2005
ACM
146views Education» more  SIGCSE 2005»
16 years 1 months ago
Using image processing projects to teach CS1 topics
As Computer Science educators, we know that students learn more from projects that are fun and challenging, that seem “real” to them, and that allow them to be creative in des...
Richard Wicentowski, Tia Newhall
251
Voted
CP
2005
Springer
16 years 1 months ago
Planning and Scheduling to Minimize Tardiness
We combine mixed integer linear programming (MILP) and constraint programming (CP) to minimize tardiness in planning and scheduling. Tasks are allocated to facilities using MILP an...
John N. Hooker
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