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ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
16 years 24 days ago
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-d...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H...
191
Voted
ISCA
2003
IEEE
116views Hardware» more  ISCA 2003»
16 years 24 days ago
A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay
Debuggers have been proven indispensable in improving software reliability. Unfortunately, on most real-life software, debuggers fail to deliver their most essential feature — a...
Min Xu, Rastislav Bodík, Mark D. Hill
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
16 years 24 days ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
RTSS
2003
IEEE
16 years 24 days ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
VL
2003
IEEE
128views Visual Languages» more  VL 2003»
16 years 24 days ago
A visual approach to development of web services providers/requestors
An idea of automatic generation of Web applications from templates has been proposed [1, 2, 3, 4]. A software system called T-Web system has been implemented based on the idea to ...
Kornkamol Jamroendararasame, Takehiro Tokuda, Tets...
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