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DFT
1999
IEEE
119views VLSI» more  DFT 1999»
15 years 11 months ago
RAMSES: A Fast Memory Fault Simulator
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some wellknown memory ...
Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
208
Voted
VRML
1999
ACM
15 years 11 months ago
A VRML Integration Methodology for Manufacturing Applications
This paper describes several methods for using the Virtual Reality Modeling Language (VRML) as the visualization integration technology for manufacturing simulation systems. One o...
Sandy Ressler, Afzal Godil, Qiming Wang, Gregory S...
VRST
1999
ACM
15 years 11 months ago
Distributed Open Inventor: a practical approach to distributed 3D graphics
Distributed Open Inventor is an extension to the popular Open Inventor toolkit for interactive 3D graphics. The toolkit is extended with the concept of a distributed shared scene ...
Gerd Hesina, Dieter Schmalstieg, Anton L. Fuhrmann...
ICCD
1999
IEEE
115views Hardware» more  ICCD 1999»
15 years 11 months ago
Customization of a CISC Processor Core for Low-Power Applications
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong...
ICPP
1999
IEEE
15 years 11 months ago
Trace-Level Reuse
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...
Antonio González, Jordi Tubella, Carlos Mol...
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