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MICRO
1997
IEEE
141views Hardware» more  MICRO 1997»
15 years 11 months ago
Unroll-and-Jam Using Uniformly Generated Sets
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
Steve Carr, Yiping Guan
DAC
1997
ACM
15 years 11 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
15 years 11 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
ICCAD
1996
IEEE
141views Hardware» more  ICCAD 1996»
15 years 11 months ago
An observability-based code coverage metric for functional simulation
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer
191
Voted
ICPP
1996
IEEE
15 years 11 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
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