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PDP
2010
IEEE
16 years 19 days ago
Load Balancing Algorithms with Partial Information Management for the DLML Library
Abstract—Load balancing algorithms are an essential component of parallel computing reducing the response time of applications. Frequently, balancing algorithms have a centralize...
Juan Santana-Santana, Miguel A. Castro-Garcí...
WISEC
2010
ACM
16 years 18 days ago
Zeroing-in on network metric minima for sink location determination
The locations of base stations are critically important to the viability of wireless sensor networks. In this paper, we examine the location privacy problem from both the attack a...
Zhenhua Liu, Wenyuan Xu
ACSC
2003
IEEE
16 years 18 days ago
Self-Adaptive Clock Synchronization Based on Clock Precision Difference
This paper presents an innovative strategy to synchronize all virtual clocks in asynchronous Internet environments. Our model is based on the architecture of one reference clock a...
Ying Zhao, Wanlei Zhou, Elicia Lanham, Shui Yu, Mi...
CODES
2003
IEEE
16 years 18 days ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
DATE
2003
IEEE
124views Hardware» more  DATE 2003»
16 years 18 days ago
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
– Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global flo...
Wonjoon Choi, Kia Bazargan
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