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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
FSTTCS
2005
Springer
16 years 28 days ago
Testing Concurrent Systems: An Interpretation of Intuitionistic Logic
Abstract. We present a natural confluence of higher-order hereditary Harrop formulas (HH formulas), Constraint Logic Programming (CLP, [JL87]), and Concurrent Constraint Programmi...
Radha Jagadeesan, Gopalan Nadathur, Vijay A. Saras...
ISSTA
2004
ACM
16 years 26 days ago
Testing of java web services for robustness
This paper presents a new compile-time analysis that enables a testing methodology for white-box coverage testing of error recovery code (i.e., exception handlers) in Java web ser...
Chen Fu, Barbara G. Ryder, Ana Milanova, David Won...
JOT
2007
123views more  JOT 2007»
15 years 7 months ago
Towards a Tool Supporting Integration Testing of Aspect-Oriented Programs
Aspect-Oriented Programming is an emerging software engineering paradigm. It offers new constructs and tools improving separation of crosscutting concerns into single units called...
Philippe Massicotte, Linda Badri, Mourad Badri
VL
2003
IEEE
126views Visual Languages» more  VL 2003»
16 years 21 days ago
Generalizing WYSIWYT visual testing to screen transition languages
ct How can rigorous forms of testing be supported in a way that is both compatible with the visual aspect of visual programming languages, and usable by the audiences using those l...
Darren Brown, Margaret M. Burnett, Gregg Rothermel...