5762 search results - page 420 / 1153 » R-tree: A Hardware Implementation |
175
click to vote
ARC
2009
Springer
16 years 9 days ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
170
click to vote
FPL
2001
Springer
16 years 4 days ago
2001
Springer
Asynchronous logic design has been around for decades. However, only recently has it gained any commercial success. Research has focused on a wide variety of uses, from microproces...
169
click to vote
ICES
2001
Springer
16 years 3 days ago
2001
Springer
Abstract. Embryonics is a long-term research project attempting to draw inspiration from the biological process of ontogeny, to implement novel digital computing machines endowed w...
159
click to vote
ASYNC
2000
IEEE
16 years 2 days ago
2000
IEEE
This paper presents several new asynchronous FIFO designs. While most existing FIFO’s trade higher throughput for higher latency, our goal is to achieve very low latency while m...
194
click to vote
DATE
2000
IEEE
16 years 2 days ago
2000
IEEE
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...