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157
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ISCAS
1999
IEEE
100views Hardware» more  ISCAS 1999»
15 years 12 months ago
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis
This paper presents the design consideration of high order digital AZ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (M...
Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud...
ISCAS
1999
IEEE
87views Hardware» more  ISCAS 1999»
15 years 12 months ago
Asymptotical optimality of DFT based DMT transceivers
The DMT (discrete multitone modulation) technique has been widely applied to data transmission over fading channels of twisted pairs. It has been shown that the DMT system with id...
Yuan-Pei Lin, See-May Phoong
CODES
1998
IEEE
15 years 12 months ago
Communication synthesis and HW/SW integration for embedded system design
The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hardware accelerators) in one system. Interfacing hardwar...
Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pega...
207
Voted
ISMVL
1998
IEEE
113views Hardware» more  ISMVL 1998»
15 years 12 months ago
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode ...
Ali Sheikholeslami, R. Yoshimura, P. Glenn Gulak
CAV
1998
Springer
108views Hardware» more  CAV 1998»
15 years 12 months ago
Decomposing the Proof of Correctness of pipelined Microprocessors
We present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction funct...
Ravi Hosabettu, Mandayam K. Srivas, Ganesh Gopalak...