7 search results - page 2 / 2 » Re-engineering of timing constrained placements for regular ... |
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ISPD
2003
ACM
15 years 11 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
247
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SIGCOMM
1998
ACM
15 years 10 months ago
1998
ACM
Several recent proposals for an “active networks” architecture advocate the placement of user-defined computation within the network as a key mechanism to enable a wide range...