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ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
16 years 12 days ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ICS
2011
Tsinghua U.
14 years 10 months ago
High performance linpack benchmark: a fault tolerant implementation without checkpointing
The probability that a failure will occur before the end of the computation increases as the number of processors used in a high performance computing application increases. For l...
Teresa Davies, Christer Karlsson, Hui Liu, Chong D...
ET
2007
101views more  ET 2007»
15 years 6 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
INFOCOM
2006
IEEE
16 years 25 days ago
DFT-MSN: The Delay/Fault-Tolerant Mobile Sensor Network for Pervasive Information Gathering
Abstract— This paper focuses on the Delay/Fault-Tolerant Mobile Sensor Network (DFT-MSN) for pervasive information gathering. We develop simple and efficient data delivery schem...
Yu Wang, Hongyi Wu
OSDI
2006
ACM
16 years 7 months ago
HQ Replication: A Hybrid Quorum Protocol for Byzantine Fault Tolerance
There are currently two approaches to providing Byzantine-fault-tolerant state machine replication: a replica-based approach, e.g., BFT, that uses communication between replicas t...
James A. Cowling, Daniel S. Myers, Barbara Liskov,...