Sciweavers

339 search results - page 64 / 68
» Reducing Memory Ordering Overheads in Software Transactional...
Sort
View
COMPSAC
2002
IEEE
15 years 11 months ago
Design and Implementation of a Network Application Architecture for Thin Clients
This paper explores the issues and the techniques of enabling multimedia applications for the thin client computing. A prototype of a video communication system based on H.323 fam...
Chia-Chen Kuo, Ping Ting, Ming-Syan Chen, Jeng-Chu...
ASPLOS
2010
ACM
16 years 1 months ago
Flexible architectural support for fine-grain scheduling
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis
INFOCOM
2008
IEEE
16 years 25 days ago
Live Baiting for Service-Level DoS Attackers
Abstract. Denial-of-Service (DoS) attacks remain a challenging problem in the Internet. In a DoS attack the attacker is attempting to make a resource unavailable to its intended le...
Sherif M. Khattab, Sameh Gobriel, Rami G. Melhem, ...
148
Voted
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
16 years 23 days ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
CN
2008
162views more  CN 2008»
15 years 6 months ago
A cache-based internet protocol address lookup architecture
This paper proposes a novel Internet Protocol (IP) packet forwarding architecture for IP routers. This architecture is comprised of a non-blocking Multizone Pipelined Cache (MPC) ...
Soraya Kasnavi, Paul Berube, Vincent C. Gaudet, Jo...