6568 search results - page 343 / 1314 » Reducing the Complexity of Reductions |
203
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INTEGRATION
2007
15 years 7 months ago
2007
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
187
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DAC
2008
ACM
16 years 8 months ago
2008
ACM
A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to differ...
219
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ISLPED
2003
ACM
16 years 23 days ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
196
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NIPS
2004
15 years 9 months ago
2004
It has been suggested that the primary goal of the sensory system is to represent input in such a way as to reduce the high degree of redundancy. Given a noisy neural representati...
172
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WIS
2004
15 years 9 months ago
2004
Modern databases allow mobile clients that subscribe to replicated data, to process the replica without requiring continuous connectivity, and to receive the updates while connecte...