6568 search results - page 349 / 1314 » Reducing the Complexity of Reductions |
158
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ISCAS
2005
IEEE
16 years 1 months ago
2005
IEEE
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
148
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ISCAS
2005
IEEE
16 years 1 months ago
2005
IEEE
—This paper proposes a programmable geometry engine (GE) reducing the expensive internal buffers and register files of the conventional programmable GEs and sharing datapaths of ...
197
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ISVLSI
2003
IEEE
16 years 25 days ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
175
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DOCENG
2003
ACM
16 years 25 days ago
2003
ACM
As Adobe's Portable Document Format has exploded in popularity so too has the number PDF generators, and predictably the quality of generated PDF varies considerably. This pa...
173
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ISLPED
2003
ACM
16 years 25 days ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...