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IJPP
2000
94views more  IJPP 2000»
15 years 7 months ago
Path Analysis and Renaming for Predicated Instruction Scheduling
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
TCAD
2002
134views more  TCAD 2002»
15 years 7 months ago
DS-LFSR: a BIST TPG for low switching activity
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
Seongmoon Wang, Sandeep K. Gupta
SIGMETRICS
2011
ACM
198views Hardware» more  SIGMETRICS 2011»
14 years 10 months ago
Greening geographical load balancing
Energy expenditure has become a significant fraction of data center operating costs. Recently, “geographical load balancing” has been suggested to reduce energy cost by explo...
Zhenhua Liu, Minghong Lin, Adam Wierman, Steven H....
SIGIR
2012
ACM
13 years 10 months ago
Parallelizing ListNet training using spark
As ever-larger training sets for learning to rank are created, scalability of learning has become increasingly important to achieving continuing improvements in ranking accuracy [...
Shilpa Shukla, Matthew Lease, Ambuj Tewari
ICIP
2009
IEEE
16 years 8 months ago
Efficiency Improvements For A Geometric-partition-based Video Coder
H.264/AVC has brought an important increase in coding efficiency in comparison to previous video coding standards. One of its features is the use of macroblock partitioning in a t...