6568 search results - page 380 / 1314 » Reducing the Complexity of Reductions |
173
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ITC
2002
IEEE
16 years 16 days ago
2002
IEEE
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...
208
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GECCO
2006
Springer
15 years 11 months ago
2006
Springer
In this paper, we propose a dynamic mechanism to vary the probability by which fitness inheritance is applied throughout the run of a multi-objective particle swarm optimizer, in ...
230
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DAC
1997
ACM
15 years 11 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
177
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ISLPED
1995
ACM
15 years 11 months ago
1995
ACM
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
204
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DELTA
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but explo...