6568 search results - page 389 / 1314 » Reducing the Complexity of Reductions |
172
Voted
ICCAD
1996
IEEE
15 years 12 months ago
1996
IEEE
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
217
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ICCAD
1996
IEEE
15 years 12 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
168
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ATS
2004
IEEE
15 years 11 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
184
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DSD
2004
IEEE
15 years 11 months ago
2004
IEEE
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transit...
204
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DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...