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VLSID
2001
IEEE
200views VLSI» more  VLSID 2001»
16 years 7 months ago
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
16 years 7 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
DATE
2008
IEEE
134views Hardware» more  DATE 2008»
16 years 1 months ago
Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence
This paper presents a novel architecture for on-chip neural network training using particle swarm optimization (PSO). PSO is an evolutionary optimization algorithm with a growing ...
Amin Farmahini Farahani, Seid Mehdi Fakhraie, Saee...
HICSS
2006
IEEE
170views Biometrics» more  HICSS 2006»
16 years 1 months ago
A Complex Adaptive System Perspective of Enterprise Architecture in Electronic Government
Within the public sector, the deployment of enterprise architecture is often an attempt to address the decentralization/centralization relationships to improve the links between t...
Marijn Janssen, George Kuk
IROS
2006
IEEE
134views Robotics» more  IROS 2006»
16 years 1 months ago
ADE: A Framework for Robust Complex Robotic Architectures
— Robots that can interact naturally with humans require the integration and coordination of many different components with heavy computational demands. We argue that an architec...
James F. Kramer, Matthias Scheutz