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» Requirements, Architectures and Risks
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189
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DATE
2006
IEEE
159views Hardware» more  DATE 2006»
16 years 1 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
16 years 1 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
158
Voted
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
16 years 1 months ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman
COMPSAC
2005
IEEE
16 years 22 days ago
Reasoning About Software Architecture-Based Regression Testing Through a Case Study
Two main issues need to be covered when dealing with the dependability of component-based systems: quality assurance of reusable software components and quality assurance of the a...
Henry Muccini, Marcio S. Dias, Debra J. Richardson
ICDE
2005
IEEE
107views Database» more  ICDE 2005»
16 years 21 days ago
Implementation of an Agent Architecture for Automated Index Tuning
It has been important to extend database management systems to support new requirements of applications and administration. We focus in this paper on the automatic tuning feature,...
Rogério Luís de Carvalho Costa, S&ea...