Sciweavers

6147 search results - page 220 / 1230
» Requirements, Architectures and Risks
Sort
View
ENTCS
2008
89views more  ENTCS 2008»
15 years 7 months ago
Dataflow Architectures for GALS
In Kahn process network (KPN), the processes (nodes) communicate by unbounded unidirectional FIFO channels (arcs), with the property of non-blocking writes and blocking reads on t...
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
CJ
2004
93views more  CJ 2004»
15 years 7 months ago
An Architecture for Kernel-Level Verification of Executables at Run Time
Digital signatures have been proposed by several researchers as a way of preventing execution of malicious code. In this paper we propose a general architecture for performing the...
Luigi Catuogno, Ivan Visconti
WINET
2002
98views more  WINET 2002»
15 years 6 months ago
A Unified Architecture for the Design and Evaluation of Wireless Fair Queueing Algorithms
Abstract. Fair queueing in the wireless domain poses significant challenges due to unique issues in the wireless channel such as locationdependent and bursty channel errors. In thi...
Thyagarajan Nandagopal, Songwu Lu, Vaduvur Bhargha...
DSD
2010
IEEE
149views Hardware» more  DSD 2010»
15 years 5 months ago
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures
Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace i...
Marcus Jeitler, Jakob Lechner
VLSISP
2011
241views Database» more  VLSISP 2011»
15 years 2 months ago
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...
Gustavo A. Ruiz, Juan A. Michell