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DAC
2003
ACM
16 years 8 months ago
Instruction encoding synthesis for architecture exploration using hierarchical processor models
This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...
Achim Nohl, Volker Greive, Gunnar Braun, Andreas H...
SASP
2009
IEEE
170views Hardware» more  SASP 2009»
16 years 1 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
ICSR
2009
Springer
16 years 1 months ago
Reuse of Architectural Knowledge in SPL Development
Abstract. Software Product Lines (SPL) promote reuse within an application domain in an organized fashion. Preimplemented software components are arranged according to a product li...
Pedro O. Rossel, Daniel Perovich, M. Cecilia Basta...
ICCCN
2008
IEEE
16 years 1 months ago
Group-Oriented Communication: Concept and Network Architecture
—In this paper, we propose a novel communication paradigm called group-oriented communication. Different from conventional unicast-based communications, group-oriented communicat...
Yousuke Takahashi, Kouhei Sugiyama, Hiroyuki Ohsak...
IPPS
2008
IEEE
16 years 1 months ago
Design of steering vectors for dynamically reconfigurable architectures
An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well ...
Nick A. Mould, Brian F. Veale, John K. Antonio, Mo...