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ICIP
1999
IEEE
16 years 8 months ago
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform
In this paper, we present a VLSI architecture for separable 2-D Discrete Wavelet Transform (DWT). Based on 1-D DWT Recursive Pyramid Algorithm (RPA), a complete 2-D DWT output sch...
Wen-Shiaw Peng, Chen-Yi Lee
VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
16 years 7 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
HPCA
2001
IEEE
16 years 7 months ago
An Architectural Evaluation of Java TPC-W
The use of the Java programming language for implementing server-side application logic is increasing in popularity, yet there is very little known about the architectural require...
Harold W. Cain, Ravi Rajwar, Morris Marden, Mikko ...
ICSE
2004
IEEE-ACM
16 years 7 months ago
A Hybrid Architectural Style for Distributed Parallel Processing of Generic Data Streams
Immersive, interactive applications grouped under the concept of Immersipresence require on-line processing and mixing of multimedia data streams and structures. One critical issu...
Alexandre R. J. François
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
16 years 4 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda