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ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
16 years 26 days ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
AIED
2005
Springer
16 years 26 days ago
THESPIAN: An Architecture for Interactive Pedagogical Drama
Interactive drama is increasingly being used as a pedagogical tool in a wide variety of computer-based learning environments. However, the effort required to build interactive dram...
Mei Si, Stacy C. Marsella, David V. Pynadath
ICS
2005
Tsinghua U.
16 years 24 days ago
A heterogeneously segmented cache architecture for a packet forwarding engine
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
Kaushik Rajan, Ramaswamy Govindarajan
WMPI
2004
ACM
16 years 22 days ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
DSRT
2003
IEEE
16 years 18 days ago
An Agent Architecture for Network Support of Distributed Simulation Systems
Continued research into distributed agent-based systems and evolving web based technologies are opening up tremendous possibilities for the deployment of large scale and highly ex...
Robert Simon, Woan Sun Chang, J. Mark Pullen