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FPGA
2005
ACM
105views FPGA» more  FPGA 2005»
16 years 23 days ago
Soft error rate estimation and mitigation for SRAM-based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
CHI
2007
ACM
16 years 7 months ago
Authoring sensor-based interactions by demonstration with direct manipulation and pattern recognition
Sensors are becoming increasingly important in interaction design. Authoring a sensor-based interaction comprises three steps: choosing and connecting the appropriate hardware, cr...
Björn Hartmann, Leith Abdulla, Manas Mittal, ...
ICCD
2004
IEEE
112views Hardware» more  ICCD 2004»
16 years 4 months ago
An Infrastructure IP for On-Chip Clock Jitter Measurement
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
Jui-Jer Huang, Jiun-Lang Huang
ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
16 years 4 months ago
Variability and yield improvement: rules, models, and characterization
Yield and variability are becoming detractors for successful design in sub-90-nm process technologies. We consider the fundamental lithography and process issues that are driving ...
Kenneth L. Shepard, Daniel N. Maynard
ITC
2002
IEEE
99views Hardware» more  ITC 2002»
16 years 4 days ago
Verifying Properties Using Sequential ATPG
This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped int...
Jacob A. Abraham, Vivekananda M. Vedula, Daniel G....