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» Reuse Technique in Hardware Design
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SIGMETRICS
2008
ACM
15 years 7 months ago
Ironmodel: robust performance models in the wild
Traditional performance models are too brittle to be relied on for continuous capacity planning and performance debugging in many computer systems. Simply put, a brittle model is ...
Eno Thereska, Gregory R. Ganger
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
15 years 7 months ago
Non-Inclusion Property in Multi-Level Caches Revisited
The center of gravity of computer architecture is moving toward memory systems. Barring breakthrough microarchitectural techniques to move processor performance to higher levels, ...
Mohamed M. Zahran, Kursad Albayraktaroglu, Manoj F...
CODES
2011
IEEE
14 years 6 months ago
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
Reliability is a major requirement for most safety-related systems. To meet this requirement, fault-tolerant techniques such as hardware replication and software re-execution are ...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
16 years 4 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
16 years 4 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani