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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 10 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
15 years 4 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu
177
Voted
DAC
2001
ACM
16 years 8 months ago
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook K...
197
Voted
EUROMICRO
2009
IEEE
16 years 1 months ago
Bridging the Component-Based and Service-Oriented Worlds
Abstract—The component-based and service-oriented development have become commonly used techniques for building high quality, evolvable, large systems in a timely and affordable ...
Karel Masek, Petr Hnetynka, Tomás Bures
130
Voted
DFT
2008
IEEE
82views VLSI» more  DFT 2008»
16 years 1 months ago
Selective Hardening of NanoPLA Circuits
Nanoelectronic components are expected to suffer from very high error rates, implying the need for hardening techniques. We propose a fine-grained approach to harden a promising...
Ilia Polian, Wenjing Rao