2778 search results - page 423 / 556 » Reuse Technique in Hardware Design |
162
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ASPDAC
2006
ACM
16 years 29 days ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
194
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ASPDAC
2006
ACM
16 years 29 days ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
188
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ASPDAC
2006
ACM
16 years 29 days ago
2006
ACM
– In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dom...
146
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ISCAS
2005
IEEE
16 years 17 days ago
2005
IEEE
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
133
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ISCAS
2005
IEEE
16 years 17 days ago
2005
IEEE
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...