2778 search results - page 426 / 556 » Reuse Technique in Hardware Design |
166
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DFT
2003
IEEE
16 years 8 days ago
2003
IEEE
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
101
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ISCAS
2003
IEEE
16 years 7 days ago
2003
IEEE
This paper describes a design of time-to-digital converter (TDC), which has the features of high-resolution and fast Conversion. With the aid of the gate delay difference techniqu...
203
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IEEEPACT
2002
IEEE
15 years 12 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
171
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CDC
2009
IEEE
15 years 11 months ago
2009
IEEE
Abstract— Commonly, controllers for Linear ParameterVarying (LPV) systems are designed in continuous-time using a Linear Fractional Representation (LFR) of the plant. However, th...
178
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APCSAC
2000
IEEE
15 years 11 months ago
2000
IEEE
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...