Sciweavers

2778 search results - page 427 / 556
» Reuse Technique in Hardware Design
Sort
View
DFT
1998
IEEE
88views VLSI» more  DFT 1998»
15 years 11 months ago
Characterization of CMOS Defects using Transient Signal Analysis
We present the results of hardware experiments designed to determine the relative contribution of CMOS coupling mechanisms to off-path signal variations caused by common types of ...
James F. Plusquellic, Donald M. Chiarulli, Steven ...
166
Voted
LATIN
1998
Springer
15 years 11 months ago
Dynamic Packet Routing on Arrays with Bounded Buffers
We study the performance of packet routing on arrays (or meshes) with bounded buffers in the routing switches, assuming that new packets are continuously inserted at all the nodes....
Andrei Z. Broder, Alan M. Frieze, Eli Upfal
160
Voted
VLSID
1993
IEEE
133views VLSI» more  VLSID 1993»
15 years 11 months ago
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
V. Visvanathan, Nibedita Mohanty, S. Ramanathan
CCL
1994
Springer
15 years 11 months ago
Application of Constraint Logic Programming for VLSI CAD Tools
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
Renate Beckmann, Ulrich Bieker, Ingolf Markhof
176
Voted
DEXA
2004
Springer
83views Database» more  DEXA 2004»
15 years 10 months ago
Efficient Rule Base Verification Using Binary Decision Diagrams
As their field of application has evolved and matured, the importance of verifying knowledge-based systems is now widely recognized. Nevertheless, some problems have remained. In t...
Christophe Mues, Jan Vanthienen