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» Reuse Technique in Hardware Design
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196
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MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
16 years 1 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
194
Voted
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
16 years 1 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
163
Voted
ASPDAC
2000
ACM
102views Hardware» more  ASPDAC 2000»
15 years 11 months ago
A hybrid approach for core-based system-level power modeling
Reducing power consumption has become a key goal for systemon-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction...
Tony Givargis, Frank Vahid, Jörg Henkel
ISLPED
2010
ACM
204views Hardware» more  ISLPED 2010»
15 years 7 months ago
Maximum power transfer tracking for a photovoltaic-supercapacitor energy system
It is important to maintain high efficiency when charging electrical energy storage elements so as to achieve holistic optimization from an energy generation source (e.g., a solar...
Younghyun Kim, Naehyuck Chang, Yanzhi Wang, Massou...
CG
2007
Springer
15 years 7 months ago
An evaluation of user experience with a sketch-based 3D modeling system
With the availability of pen-enabled digital hardware, sketch-based 3D modeling is becoming an increasingly attractive alternative to traditional methods in many design environmen...
Levent Burak Kara, Kenji Shimada, Sarah D. Marmale...