2778 search results - page 439 / 556 » Reuse Technique in Hardware Design |
192
click to vote
ICCD
2002
IEEE
16 years 3 months ago
2002
IEEE
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
168
click to vote
ICCD
2002
IEEE
16 years 3 months ago
2002
IEEE
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
176
click to vote
ICCD
2001
IEEE
16 years 3 months ago
2001
IEEE
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
192
click to vote
ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
—SystemC is a system-level modeling language that offers a wide range of features to describe concurrent systems rent levels of abstraction. The SystemC standard permits simulato...
166
click to vote
ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...