2778 search results - page 440 / 556 » Reuse Technique in Hardware Design |
193
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
176
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ICCAD
2004
IEEE
16 years 3 months ago
2004
IEEE
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
182
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
159
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—Caches often employ write-back instead of writethrough, since write-back avoids unnecessary transfers for multiple writes to the same block. For several reasons, however...
182
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
— During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builti...