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DATE
2008
IEEE
117views Hardware» more  DATE 2008»
16 years 1 months ago
A Scalable Algorithmic Framework for Row-Based Power-Gating
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
16 years 1 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
DATE
2008
IEEE
111views Hardware» more  DATE 2008»
16 years 1 months ago
A Formal Approach To The Protocol Converter Problem
In the absence of a single module interface standard, integration of pre-designed modules in System-on-Chip design often requires the use of protocol converters. Existing approach...
Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Rames...
ISCAS
2008
IEEE
110views Hardware» more  ISCAS 2008»
16 years 1 months ago
Distortion calculation of an asynchronous switching xDSL line-driver
Abstract—Since the xDSL specifications impose stringent linearity requirements to ensure the integrity of the data transferred, current line drivers use linear amplifiers. The do...
Vincent De Gezelle, Jordie Buyle, Jan Doutreloigne
MOMPES
2008
IEEE
16 years 1 months ago
Architectural Concurrency Equivalence with Chaotic Models
During its lifetime, embedded systems go through multiple changes to their runtime architecture. That is, threads, processes, and processor are added or removed to/from the softwa...
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