2778 search results - page 449 / 556 » Reuse Technique in Hardware Design |
174
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DATE
2002
IEEE
15 years 12 months ago
2002
IEEE
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
120
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
We present a CMOS circuit that utilizes the back-gate effect to extend the linear range of a subthreshold MOS transconductor. Previous designs of wide-linear-range transconductors...
191
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
174
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ISQED
2002
IEEE
15 years 11 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
147
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...