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» Reuse Technique in Hardware Design
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ASPDAC
2007
ACM
132views Hardware» more  ASPDAC 2007»
15 years 11 months ago
FastRoute 2.0: A High-quality and Efficient Global Router
Because of the increasing dominance of interconnect issues in advanced IC technology, it is desirable to incorporate global routing into early design stages to get accurate interco...
Min Pan, Chris C. N. Chu
CASES
2009
ACM
15 years 11 months ago
Exploiting residue number system for power-efficient digital signal processing in embedded processors
2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propaga...
Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shr...
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 10 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
GLVLSI
2009
IEEE
146views VLSI» more  GLVLSI 2009»
15 years 10 months ago
A reconfigurable stochastic architecture for highly reliable computing
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan...
ASAP
2004
IEEE
119views Hardware» more  ASAP 2004»
15 years 10 months ago
Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators
Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. Th...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott...