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CODES
2008
IEEE
16 years 2 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
CODES
2007
IEEE
16 years 2 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
CODES
2006
IEEE
16 years 1 months ago
Battery discharge aware energy feasibility analysis
It is observed that pulsed discharge currents allow to drain the battery with a higher specific power. Thus they improve the batteries durability and discharge performance. The q...
Henrik Lipskoch, Karsten Albers, Frank Slomka
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
16 years 1 months ago
Silicon neurons that phase-lock
Abstract—We present a silicon neuron with a dynamic, active leak that enables precise spike-timing with respect to a time-varying input signal. Our neuron models the mammalian bu...
J. H. Wittig Jr., Kwabena Boahen
CODES
2005
IEEE
16 years 1 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
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