Sciweavers

7262 search results - page 1261 / 1453
» Reversible Computer Hardware
Sort
View
IEEEPACT
2005
IEEE
16 years 18 days ago
A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction
The continual demand for greater performance and growing concerns about the power consumption in highperformance microprocessors make the branch predictor a critical component of ...
Gabriel H. Loh
170
Voted
IEEEPACT
2005
IEEE
16 years 18 days ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
198
Voted
IEEEPACT
2005
IEEE
16 years 18 days ago
Communication Optimizations for Fine-Grained UPC Applications
Global address space languages like UPC exhibit high performance and portability on a broad class of shared and distributed memory parallel architectures. The most scalable applic...
Wei-Yu Chen, Costin Iancu, Katherine A. Yelick
IEEEPACT
2005
IEEE
16 years 18 days ago
Memory Coloring: A Compiler Approach for Scratchpad Memory Management
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
Lian Li 0002, Lin Gao 0002, Jingling Xue
IEEEPACT
2005
IEEE
16 years 18 days ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...
« Prev « First page 1261 / 1453 Last » Next »