116 search results - page 9 / 24 » Route Packets, Not Wires: On-Chip Interconnection Networks |
165
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ICC
2007
IEEE
16 years 27 days ago
2007
IEEE
—A new network architecture for high-speed low-latency interconnects is introduced, based on a combination of optical wavelength division multiplexing and the automatic packet se...
162
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
172
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HPCA
2009
IEEE
16 years 1 months ago
2009
IEEE
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
168
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
142
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EUROPAR
2001
Springer
15 years 11 months ago
2001
Springer
We present randomized and deterministic algorithms for many-to-one routing on an n-node two-dimensional mesh under the store-and-forward model of packet routing. We consider the g...