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DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 11 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
EH
2004
IEEE
110views Hardware» more  EH 2004»
15 years 11 months ago
A Genetic Algorithm for the Optimisation of a Reconfigurable Pipelined FFT Processor
This paper describes the optimisation of the word length in a 16-point radix-4 reconfigurable pipelined Fast Fourier Transform (FFT) based receiver device. Two forms of optimisati...
Nasri Sulaiman, Tughrul Arslan
COORDINATION
2006
Springer
15 years 11 months ago
Synthesizing Concurrency Control Components from Process Algebraic Specifications
Process algebraic specifications can provide useful support for the architectural design of software systems due to the possibility of analyzing their properties. In addition to th...
Edoardo Bontà, Marco Bernardo, Jeff Magee, ...
DSVIS
2006
Springer
15 years 11 months ago
Toward Quality-Driven Development of 3D Computer Games
The development of video games is a complex software engineering activity bringing together large multidisciplinary teams under stringent constraints. While much has been written a...
T. C. Nicholas Graham, Will Roberts
EDBTW
2006
Springer
15 years 11 months ago
Semantically Correct Query Answers in the Presence of Null Values
For several reasons a database may not satisfy a given set of integrity constraints (ICs), but most likely most of the information in it is still consistent with those ICs; and cou...
Loreto Bravo, Leopoldo E. Bertossi