433 search results - page 25 / 87 » Scale in Chip Interconnect requires Network Technology |
191
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ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
168
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DAC
2010
ACM
15 years 8 months ago
2010
ACM
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
154
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ISCA
2007
IEEE
16 years 27 days ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
150
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ISLPED
2009
ACM
16 years 1 months ago
2009
ACM
This paper presents an evaluation to determine the importance of the accurate thermal characterization for several elements of a semiconductor device. Specifically, it evaluates ...
153
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptima...