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ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
16 years 1 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...
191
Voted
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
16 years 1 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
IDEAL
2004
Springer
16 years 9 days ago
Combining Local and Global Models to Capture Fast and Slow Dynamics in Time Series Data
Many time series exhibit dynamics over vastly different time scales. The standard way to capture this behavior is to assume that the slow dynamics are a “trend”, to de-trend t...
Michael Small
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
16 years 1 days ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
CLOUD
2010
ACM
16 years 1 days ago
A self-organized, fault-tolerant and scalable replication scheme for cloud storage
Failures of any type are common in current datacenters, partly due to the higher scales of the data stored. As data scales up, its availability becomes more complex, while differe...
Nicolas Bonvin, Thanasis G. Papaioannou, Karl Aber...