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EDCC
1999
Springer
15 years 11 months ago
A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators
In this paper we present a new fault tolerant clock synchronization algorithm called the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of...
Henrik Lönn
ICECCS
1998
IEEE
161views Hardware» more  ICECCS 1998»
15 years 11 months ago
A Method and a Technique to Model and Ensure Timeliness in Safety Critical Real-Time Systems
The main focus of this paper is the problem of ensuring timeliness in safety critical systems. First, we introduce a method and its associated technique to model both real-time ta...
Christophe Aussaguès, Vincent David
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
15 years 11 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
15 years 11 months ago
Efficient BMC for Multi-Clock Systems with Clocked Specifications
- Current industry trends in system design -- multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with...
Malay K. Ganai, Aarti Gupta
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 9 months ago
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems
In this paper, we propose a simulation-based methodology for worst-case response time estimation of distributed realtime systems. Schedulability analysis produces pessimistic uppe...
Soheil Samii, Sergiu Rafiliu, Petru Eles, Zebo Pen...